summaryrefslogtreecommitdiff
path: root/doc/assignment1.md
blob: 2ac5617de61d199729243153cc1388aa7d37218e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
# Assignment 1

This assignment should be submitted after you have finished Unit 1. It is worth 10% of your final grade.

## Part 1: Concepts and Principles (60 marks; 5 marks each)

Instructions: Please answer the following questions in complete sentences. Your answer for each question should be about 150 words.

1. Define the concepts interrupt and trap, and explain the purpose of an interrupt vector.

    An interrupt vector is a list or table of interrupts. Each interrupt has an
    address to the interrupt routine to execute when the interrupt is signaled.
    A trap is a way to capture a triggered signal to allow programs to respond to
    and handle the signal.

    Signals can be sent to a particular process via the `kill` program.
    A list of signals that can be sent are listed below:

    ```bash
    モ kill -L
    1) SIGHUP       2) SIGINT       3) SIGQUIT      4) SIGILL       5) SIGTRAP
    6) SIGABRT      7) SIGBUS       8) SIGFPE       9) SIGKILL     10) SIGUSR1
    11) SIGSEGV     12) SIGUSR2     13) SIGPIPE     14) SIGALRM     15) SIGTERM
    16) SIGSTKFLT   17) SIGCHLD     18) SIGCONT     19) SIGSTOP     20) SIGTSTP
    21) SIGTTIN     22) SIGTTOU     23) SIGURG      24) SIGXCPU     25) SIGXFSZ
    26) SIGVTALRM   27) SIGPROF     28) SIGWINCH    29) SIGIO       30) SIGPWR
    31) SIGSYS      34) SIGRTMIN    35) SIGRTMIN+1  36) SIGRTMIN+2  37) SIGRTMIN+3
    38) SIGRTMIN+4  39) SIGRTMIN+5  40) SIGRTMIN+6  41) SIGRTMIN+7  42) SIGRTMIN+8
    43) SIGRTMIN+9  44) SIGRTMIN+10 45) SIGRTMIN+11 46) SIGRTMIN+12 47) SIGRTMIN+13
    48) SIGRTMIN+14 49) SIGRTMIN+15 50) SIGRTMAX-14 51) SIGRTMAX-13 52) SIGRTMAX-12
    53) SIGRTMAX-11 54) SIGRTMAX-10 55) SIGRTMAX-9  56) SIGRTMAX-8  57) SIGRTMAX-7
    58) SIGRTMAX-6  59) SIGRTMAX-5  60) SIGRTMAX-4  61) SIGRTMAX-3  62) SIGRTMAX-2
    63) SIGRTMAX-1  64) SIGRTMAX
    ```

    Programs can also trap a signal and handle them. In the following example
    the Ruby program is trapping the `SIGUSR1` signal to reload a configuration
    file.

    ```ruby
    #!/usr/bin/env ruby

    pid = fork do
      Signal.trap("USR1") do
        puts "done"
        exit 0
      end

      loop do
        print "."
        sleep 1
      end
    end

    Process.detach(pid)
    sleep 5
    Process.kill("USR1", pid)
    ```

    When this program is run it will print a '.' 5 times and then exit.

    ```bash
    モ ruby lib/sigtrap.rb
    .....done
    ```

1. How does a computer system with von Neumann architecture execute an instruction?

    * fetch instruction from memory and store that instruction in the instruction register.
    * decode instruction. may cause operands to be fetched from memory and stored in some internal register.
    * execute instruction
    * store result back in register

    ```plaintext
                      -------------
                      | --------- |
                      | | CPU   | |
                      | | ----- | |
                      | | |CU | | |
                      | | ----- | |
      ----------      | | ----- | |       ----------
      | Input  |      | | |ALU| | | ----> | Output |
      | Device |----> | | ----- | |       | Device |
      ----------      | --------- |       ----------
                      |   |  A    |
                      |   V  |    |
                      | --------- |
                      | | MU    | |
                      | --------- |
                      -------------

     CPU: Central Processing Unit
     CU: Control Unit
     ALU: Arithmetic/Logic Unit
     MU: Memory Unit
    ```
    [source][wiki-von-neumann]

1. What role do device controllers and device drivers play in a computer system?

    Each device controller is in charge of a specific type of device.
    The device controller is responsible for moving the data between the peripheral
    devices that it controls and its local buffer storage.
    Operating systems have a device driver for each device controller. This
    device driver understands the device controller and presents a uniform
    interface to the device to the rest of the operating system.

    To start an I/O operation, the device driver loads the appropriate registers
    within the device controller. The device controller, in turn, examines the
    contents of these registers to determine what action to take. The controller
    starts the transfer of data from the device to its local buffer. Once
    the transfer of data is complete, the device controller informs the device
    driver via an interrupt that it has finished its operation. The device
    driver then returns control to the operating system, possibly returning
    the data or a pointer to the data if the operation was a read. For
    other operations, the device driver returns status information.

1. Why do clustered systems provide what is considered high-availability service?

    Clustered systems gather together multiple CPUs to accomplish computational
    work. Clustered systems differ from multiprocessor systems in that they are
    composed of two or more individual systems joined together.

    Clusted computers share storage and are closely linked via a local area network.

    A high availability service will continue even if one or more systems in the cluster
    fail. HA is generally obtained by adding a level of redundancy in the system.
    A layer of cluster software runs on the cluster nodes. Each node can monitor one or
    more of the others. If the monitored machine fails, the monitoring machine can take
    ownership of its storage and restart applications that were running on the failed machine.
    The users and clients of the applications see only a brief interruption of service.

1. Describe an operating system's two modes of operation.

    kernel mode: executes tasks on behalf of the operating system.
    user mode: executes tasks on behalf of the user.

    Whenever the operating system gains control of the computer, it is in kernel mode.
    The dual modes of operation provides a way for protecting the operating system
    from malicious behaviour. Instructions that can cause harm are treated as
    privileged instructions. Privileged instructions can only be executed in
    kernel mode.

1. Define cache, and explain cache coherency.

    The cache acts as a faster storage system that can store items on a temporary basis.
    When a piece of data is needed, the cache can be used to fetch the data once
    and stored in the cache. Subsequent attempts to access the same data can be
    fetched from the cache at a faster rate of access. Cache is meant to be temporary
    for fetching frequently used data quickly. However, the cache can become stale
    and out of sync with the backing storage from where the cache initially retrieved
    the data. Cache expiration is one of the hard problems in computer science.

    In a multitasking environment if several processes wish to access a piece of data
    then each process must access the current value of that piece of data. If that
    piece of data is stored in different caches it is possible for the same piece
    of data to have a different value if there isn't a mechanism to synchronize each
    of the caches with any mutations made to the piece of data. Cache coherency
    ensures that the data stored in different layers of cache are synchronized and
    this is typically handled in the hardware layer.

1. Describe why direct memory access (DMA) is considered an efficient mechanism for performing I/O.

    Reading data from different types of hardware can yield inconsistent I/O performance.
    It can also degrage harder at a faster rate due to increased usage. DMA allows for
    copying data from hardware into an in memory buffer that can be accessed directly.
    This allows read sequential pieces of data from the hardware less often and speeds
    up access to the data. One interrupt is generated per block rather than the one
    interrupt per byte of data read.

1. Describe why multicore processing is more efficient than placing each processor on its own chip.

    On-chip communication is faster than between-chip communication. One chip with
    multiple cores uses less power than multiple single-core chips.

1. Describe the relationship between an API, the system-call interface, and the operating system.
1. Describe some requirements and goals to consider when designing an operating system.
1. Explain why a modular kernel may be the best of the current operating system design techniques.
1. Distinguish between virtualization and simulation.

## Part 2: Design Considerations (40 marks)

Instructions: Please answer the following questions in about 1-2 pages each.

1. Draw a typical computer organization figure that includes the main components of von Neumann architecture. Identify each component, and explain its function and interaction relative to other components. (15 marks)
1. Define system call, and list the main types of system calls. Elaborate on how a system call interacts with a standard C library and hardware under a dual-mode operating system environment. (10 marks)
1. Describe the overall structure of virtual machines, and compare VMware and JVM. (15 marks)

[wiki-von-neumann]: https://en.wikipedia.org/wiki/Von_Neumann_architecture